Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits

This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirement and a lower power consumption as compared to other asynchronous solutions. It is then discussed how general purpose delay-insensitive circuits can be designed with ternary logic elements and finally an asynchronous sequence recognition circuit is described as application oj the approach. representation. In the Past, it was difficult to obtain non-trivial ternary circuits and so the investigation on asynchronous multivalued logic was discouraged [5]. Recently, improved and reliable CMOS multivalued logic has been reported [6] and its use in asynchronous circuits has been proposed [7]. This paper shows how a CMOS multivalued (ternary) logic can be employed to design delay-insensitive asynchronous circuits. The basic idea is a wire and power efficient handshake protocol that utilises transitions to the intermediate (third) logic level to separate different events. The most useful advantages of this approach are shown, the basic of the circuit design of the asynchronous ternary circuits are given and the extension to complex network design is discussed. Finailly, a case study is described: the realisation of an asynchronous sequence recognition circuit.